Static Timing Analysis

Project : SimpleSDR_Bootloader
Build Time : 03/16/12 15:20:06
Device : CY8C3866PVI-021
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 56.000 MHz 56.000 MHz N/A
CyBUS_CLK Sync 56.000 MHz 56.000 MHz N/A
CyILO Async 100.000 kHz 100.000 kHz N/A
CyIMO Async 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK Sync 56.000 MHz 56.000 MHz N/A
CyPLL_OUT Async 56.000 MHz 56.000 MHz N/A
CyXTAL Async 24.000 MHz 24.000 MHz N/A