Update: Author Gary Richardson, AA7VM, reports
that there have been some problems with excessive clock noise in generators
built from his article, "A Low DDS Function Generator" [Nov 2005, pp 40-42]. He
notes that he has been unable to entirely eliminate the noise from the outputs,
but it can be reduced quite a bit by tacking a 0.1 µF capacitor across pins 4
and 8 of U2. For best results, keep the leads as short as possible. If in your
circuit C4 and C9 are electrolytic capacitors, it may also be helpful to
replace them with tantalum capacitors.
The output must be taken from pins 1 or 7 of the op-amp
and AGND.
There should not be a connection between AGND and DGND at
the connector.
The best way to observe this noise is to set the frequency
to zero. He reports seeing about 15 mVpp spikes at the 10 MHz clock
frequency. After making these changes, noise has been reduced to about 2 mVpp.
Page last modified: 10:54 AM, 25 May 2006 ET
Page author: qst@arrl.org
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